- Products description -
XYT2840x100 module is designed for 40km optical communication applications,
and it is compliant to IEEE 802.3ba for 100GE Ethernet and ITU-T 4L1-9C1F for OTU-4. This module contains 4-lane optical transmitter, 4-lane optical receiver and module manage- ment block including 2 wire serial interface. The optical signals are multiplexed to a single- mode fiber through an industry standard LC connector. A block diagram is shown in Figure 1.
Figure 1.Transceiver Block Diagram
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire se- rial communication commands. The ModSelL allows the use of multiple modules on a single module.
In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any modules are deselected. Similarly, the host shall wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire se- rial communication commands. The ModSelL allows the use of multiple modules on a single module.
In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any modules are deselected. Similarly, the host shall wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.
The ResetL pin shall be pulled to Vcc in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the ris- ing edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by asserting "low" an IntL signal with the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.
The LPMode pin shall be pulled up to Vcc in the module. The pin is a hardware control used to put modules into a low power mode when high. By using the LPMode pin and a combina- tion of the Power override, Power_set and High_Power_Class_Enable software control bits (Address A0h, byte 93 bits 0,1,2).
ModPrsL is pulled up to Vcc_Host on the host board and grounded in the module. The Mod- PrsL is asserted "Low" when inserted and deasserted "High" when the module is physically absent from the host connector.
IntL is an output pin. When IntL is "Low", it indicates a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2- wire serial interface. The IntL pin is an open collector output and shall be pulled to host sup- ply voltage on the host board. The INTL pin is deasserted "High" after completion of reset, when byte 2 bit 0 (Data Not Ready) is read with a value of '0' and the flag field is read (see SFF-8636).
- Product Features -
QSFP28 MSA compliant
Compliant to IEEE 802.3ba 100GBASE-ER4 and OTN OTU4 4L1-9C1F
Digital diagnostic monitoring support
Hot pluggable 38 pin electrical interface
4 LAN-WDM lanes MUX/DEMUX design
4x25G electrical interface
LC duplex connector
Supports 103.125Gb/s and 111.81Gb/s aggregate bit rate
Up to 40km transmission on single mode fiber
Operating case temperature: 0℃ to 70℃
Single 3.3V power supply
RoHS-6 compliant
- Product applications -
100GBASE-ER4 100G Ethernet
OTN OTU4 4L1-9C1F
Telecom networking
Data Center Interconnect
Enterprise networking
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